STEVAL-FKI868V1 with NUCLEO-L152RE board.
Can be used “normally” or via mbed.
Sigfox page: https://partners.sigfox.com/products/steval-fki868v1
Schematics in the datasheet or here: http://www.st.com/resource/en/schematic_pack/steval-fki868v1_schematic.pdf
S2-LP ULP transceiver page: http://www.st.com/en/wireless-connectivity/s2-lp.html
STMicro Wireless Connectivity for IoT Applications Brochure: http://www.st.com/resource/en/brochure/brwireless_web.pdf
! many thanks to STMicroelectronics
STMICROELECTRONICS – ST-LINK & ST-LINK/V2 – DEBUGGER/PROGRAMMER, ICD, FOR STM8 and STM32
The ST-LINK/V2 in-circuit debugger and programmer for the STM8 and STM32 microcontroller families features a single wire interface module (SWIM) and a JTAG/serial wire debugging (SWD) interfaces are used to communicate with any STM8 or STM32 microcontroller located on an application board.
- 5 V power from USB connector, USB 2.0 full speed compatible interface
- SWIM specific features:
– 1.65 V to 5.5 V application voltage supported on SWIM interface
- JTAG/serial wire debugging (SWD) specific features:
Farnell Order Code: 1892523
- USB 2.0 full speed interface compatible
- SWIM specific features:
- 1.65 V to 5.5 V application voltage supported on SWIM interface
- SWIM low speed and high speed modes supported
- SWIM programming speed rates of 9.7 Kbytes/s in low speed, 12.8 Kbytes/s in high speed
- SWIM cable for connection to an application with an ERNI standard connector vertical (ref: 284697 or 214017) or horizontal (ref: 214012)
- SWIM cable for connection to an application with pin headers or 2.54 mm pitch connector
- JTAG/SWD specific features:
- 3 V to 3.6 V application voltage supported on JTAG/SWD interface and 5 V tolerant inputs
- JTAG/SWD cable provided for connection to a standard JTAG 20-pin pitch 2.54 mm connector
ARM® and ST Free European seminar series on the new STM32 F0 MCU series, between 22 May and 5 July 2012.
Attend this FREE seminar and walk away with in-depth technical knowledge of the STM32 F0 series and a FREE STM32 F0 Discovery Kit!
Technical Documentation and Software ST page or direct links:
- Patent Proposal Could Help EEs June 18, 2019The U.S. Congress is considering legislation on what is eligible for a patent, a bill likely to encourage or at least maintain the level of patent filings by system and chip designers.
- TSMC, Purdue Team Up to Enhance Chip Security June 18, 2019TSMC and Purdue University announced the establishment of a center at the university to enhance semiconductor security.
- Chiplet Ecosystem Slowly Picks up Steam June 18, 2019Momentum is gathering for the heterogeneous integration of chiplets from multiple vendors in a system-in-package.