J-Link Base v.9 50% off at microchipdirect.com
- TWR-K70F120M – MK70FN1M0VMJ12: K70FN1M in a 256 MAPBGA with 120 MHz operation
- TWR-ELEV – Two elevator modules that provide power regulation circuitry, standardized signal assignments, and act as common backplane for all assembled Tower System modules
- TWR-SER – Serial peripheral module with Ethernet, USB, RS232/485, and CAN interface circuitry
- J-Link Lite for Cortex-M – a small JTAG-emulator with SWD/SWO debugging support for Cortex-M devices
- DVD with software development tools, example projects & MQX BSPs, documentation
Price in IAR’s e-shop: 200 EUR / USD 249
(the link states old.iar… but is the current e-shop)
A great debug tool from one of the greatest producer priced @ 250 Euro
- Supports ARM7/ARM9/ARM11 and Cortex-M/R/A cores
- Seamless integration into the IAR Embedded Workbench IDE
- Fully plug-and-play compatible
- Hi-speed USB 2.0 interface (480Mbps)
- No power supply required, powered entirely by the USB port
- Target power of up to 400mA can be supplied from I-jet with overload protection
- Target power consumption can be measured with ~200µA resolution at 200kHz
- JTAG and Serial Wire Debug (SWD) clocks up to 32MHz (no limit on the MCU clock speed)
- Serial Wire Viewer (SWV) with UART and Manchester encoding
- Support for SWO speeds of up to 60MHz
- Embedded Trace Buffer (ETB) support
- Download speed of up to 1MByte/sec
- Automatic core recognition
- Support for multiple JTAG devices with automatic chain detection and graphical display
- Direct download into flash memory of most popular microcontrollers
- Support for JTAG adaptive clocking (RTCK)
- Automatic JTAG/SWD detection
- JTAG voltage measurement and monitoring
- Supports target voltage range from 1.65V to 5V
- Standard MIPI-20 and MIPI-10 JTAG cables are included
- ARM-20 (0.1in x 0.1in) JTAG adapter is included
The MSP-FET430UIF is a USB debugging interface used to program and debug the MSP430 through the JTAG interface or Through the 2-wire Spy Bi-Wire protocol. No external power is required.
- Software configurable supply voltage between 1.8 and 3.6 volts at 100mA
- Supports JTAG Security Fuse blow to protect code
- Supports all MSP430 boards with JTAG header
- Supports both JTAG and Spy-Bi-Wire (2-wire JTAG) debug protocols
TI Product Folder: http://www.ti.com/tool/msp-fet430uif
One of the best things is that it supports the whole range of MSP430. If you are new to MSP430 you can grab one bundled with a Target Board. TI’s Target Boards are using a very good quality ZIF socket (TSSOP, QFN, LQFP, SOIC, SSOP, … ), direct access to all chip pins, some quick configuration jumpers and a JTAG Cable Header.
MSP430 Buglist can be found here http://www.ti.com/sc/cgi-bin/buglist.cgi
The TI Engineer to Engineer (E2E) community can be found here: http://e2e.ti.com/
This development tool supports all AVR devices with JTAG Interface, from 8-bit to 32-bit AVR devices (with On-Chip Debugging).
- Supports up to 3 hardware program breakpoints or 1 maskable data breakpoint (depending on the OCD)
- Supports symbolic debug of complex data types including scope information
- Supports up to 128 software breakpoints
- Includes on-board 512kB SRAM for fast statement-level stepping
- Level converters support 1.8V to 5.5V target operation
- Uploads 256Kb code in ~30 seconds (XMEGA using JTAG interface)
- Full-speed USB 2.0 compliant (12 MB/s) and RS-232 host interfaces
Some considerations about debugging with JTAGICE from the User Guide (p.7-8, sections 1.2.2-1.2.6) download User Guide
In Run mode, the code execution is completely independent of the JTAG ICE. The JTAG ICE will continuously poll the target AVR to see if a break condition has occurred. When this happens, the OCD system will read out all necessary data Program Counter, I/O registers, EEPROM, General Purpose registers, and SRAM contents, and transmit this to AVR Studio through the JTAG interface. Since the target AVR device operates independently, there is no way of tracing what code has been executed prior to the breakpoint.
The Stopped Mode: When a breakpoint is reached, the program execution is halted, but all I/O will continue to run as if a breakpoint did not occurred. For example, assume that a USART transmit was initiated when a breakpoint is reached. Using a traditional ICE, the operation would
be halted, and single stepping through the code would give a cycle accurate bit pattern on the TxD pin. When using the JTAG ICE on the AVR, the USART would continue to run at full speed completing the transmission.
Software Breakpoints: A software breakpoint is a break instruction placed in Flash memory. When this instruction is executed, it will break the program execution. When placing a breakpoint on an instruction in AVR Studio, this instruction is physically rewritten as a break instruction in the AVR Flash memory. When reaching this instruction the operation is halted. To continue execution a “start” command has to be given from the OCD logic. When starting the execution, the instruction replaced by software break instruction is executed before continuing to execute instructions from the Flash memory.
Hardware Breakpoints: In the OCD logic there are 4 registers capable of storing one memory address each. The JTAG ICE uses one of these registers permanently to implement single stepping. The 3 others can be combined to generate valid break conditions. Section 3.2.4 describes in
detail the different ways of combining these registers. Software breakpoint require reprogramming of the entire page, hardware breakpoints
are recommended for breakpoints that are often modified.
I/O Registers: JTAG ICE has limitation in viewing the contents in all I/O locations. When an AVR device reaches a breakpoint, the contents of all I/O registers are read out and presented in AVR Studio. Reading alters the contents in some registers, these registers will not be read (e.g., Reading USART data register, will clear the RXC bit). See the “Special Considerations” section to find the complete list of registers that not are
accessible through the JTAG ICE OCD system.
Single Stepping: Some registers needs to be read or written within a specified number of cycles after a control signal is enabled. The I/O clock and peripherals continue to run at full speed in stopped mode, single stepping through such code will not meet the timing requirements. For example, when single stepping, the I/O clock might have run for millions of cycles. To read or write registers with such timing requirements, the read or write sequence should be performed as a single operation. Run the device at full speed by using a macro, function call or run-to-cursor.
For detailed information about the “JTAG Interface and On-chip Debug System” see the applicable datasheet.
STMICROELECTRONICS – ST-LINK & ST-LINK/V2 – DEBUGGER/PROGRAMMER, ICD, FOR STM8 and STM32
The ST-LINK/V2 in-circuit debugger and programmer for the STM8 and STM32 microcontroller families features a single wire interface module (SWIM) and a JTAG/serial wire debugging (SWD) interfaces are used to communicate with any STM8 or STM32 microcontroller located on an application board.
- 5 V power from USB connector, USB 2.0 full speed compatible interface
- SWIM specific features:
– 1.65 V to 5.5 V application voltage supported on SWIM interface
- JTAG/serial wire debugging (SWD) specific features:
Farnell Order Code: 1892523
- USB 2.0 full speed interface compatible
- SWIM specific features:
- 1.65 V to 5.5 V application voltage supported on SWIM interface
- SWIM low speed and high speed modes supported
- SWIM programming speed rates of 9.7 Kbytes/s in low speed, 12.8 Kbytes/s in high speed
- SWIM cable for connection to an application with an ERNI standard connector vertical (ref: 284697 or 214017) or horizontal (ref: 214012)
- SWIM cable for connection to an application with pin headers or 2.54 mm pitch connector
- JTAG/SWD specific features:
- 3 V to 3.6 V application voltage supported on JTAG/SWD interface and 5 V tolerant inputs
- JTAG/SWD cable provided for connection to a standard JTAG 20-pin pitch 2.54 mm connector
- Patent Proposal Could Help EEs June 18, 2019The U.S. Congress is considering legislation on what is eligible for a patent, a bill likely to encourage or at least maintain the level of patent filings by system and chip designers.
- TSMC, Purdue Team Up to Enhance Chip Security June 18, 2019TSMC and Purdue University announced the establishment of a center at the university to enhance semiconductor security.
- Chiplet Ecosystem Slowly Picks up Steam June 18, 2019Momentum is gathering for the heterogeneous integration of chiplets from multiple vendors in a system-in-package.