This development tool supports all AVR devices with JTAG Interface, from 8-bit to 32-bit AVR devices (with On-Chip Debugging).
- Supports up to 3 hardware program breakpoints or 1 maskable data breakpoint (depending on the OCD)
- Supports symbolic debug of complex data types including scope information
- Supports up to 128 software breakpoints
- Includes on-board 512kB SRAM for fast statement-level stepping
- Level converters support 1.8V to 5.5V target operation
- Uploads 256Kb code in ~30 seconds (XMEGA using JTAG interface)
- Full-speed USB 2.0 compliant (12 MB/s) and RS-232 host interfaces
Some considerations about debugging with JTAGICE from the User Guide (p.7-8, sections 1.2.2-1.2.6) download User Guide
In Run mode, the code execution is completely independent of the JTAG ICE. The JTAG ICE will continuously poll the target AVR to see if a break condition has occurred. When this happens, the OCD system will read out all necessary data Program Counter, I/O registers, EEPROM, General Purpose registers, and SRAM contents, and transmit this to AVR Studio through the JTAG interface. Since the target AVR device operates independently, there is no way of tracing what code has been executed prior to the breakpoint.
The Stopped Mode: When a breakpoint is reached, the program execution is halted, but all I/O will continue to run as if a breakpoint did not occurred. For example, assume that a USART transmit was initiated when a breakpoint is reached. Using a traditional ICE, the operation would
be halted, and single stepping through the code would give a cycle accurate bit pattern on the TxD pin. When using the JTAG ICE on the AVR, the USART would continue to run at full speed completing the transmission.
Software Breakpoints: A software breakpoint is a break instruction placed in Flash memory. When this instruction is executed, it will break the program execution. When placing a breakpoint on an instruction in AVR Studio, this instruction is physically rewritten as a break instruction in the AVR Flash memory. When reaching this instruction the operation is halted. To continue execution a “start” command has to be given from the OCD logic. When starting the execution, the instruction replaced by software break instruction is executed before continuing to execute instructions from the Flash memory.
Hardware Breakpoints: In the OCD logic there are 4 registers capable of storing one memory address each. The JTAG ICE uses one of these registers permanently to implement single stepping. The 3 others can be combined to generate valid break conditions. Section 3.2.4 describes in
detail the different ways of combining these registers. Software breakpoint require reprogramming of the entire page, hardware breakpoints
are recommended for breakpoints that are often modified.
I/O Registers: JTAG ICE has limitation in viewing the contents in all I/O locations. When an AVR device reaches a breakpoint, the contents of all I/O registers are read out and presented in AVR Studio. Reading alters the contents in some registers, these registers will not be read (e.g., Reading USART data register, will clear the RXC bit). See the “Special Considerations” section to find the complete list of registers that not are
accessible through the JTAG ICE OCD system.
Single Stepping: Some registers needs to be read or written within a specified number of cycles after a control signal is enabled. The I/O clock and peripherals continue to run at full speed in stopped mode, single stepping through such code will not meet the timing requirements. For example, when single stepping, the I/O clock might have run for millions of cycles. To read or write registers with such timing requirements, the read or write sequence should be performed as a single operation. Run the device at full speed by using a macro, function call or run-to-cursor.
For detailed information about the “JTAG Interface and On-chip Debug System” see the applicable datasheet.